1) Field of the Invention
This invention relates generally to fabrication of field effect transistors (FET), such as CMOS transistors, and more particularly to a method for forming field effect transistors with stressed channel regions.
2) Description of the Prior Art
It is well established that the stress/strain in the silicon channel can affect the mobility of carriers significantly. For example, tensile longitudinal stress along the device channel improves the electron mobility while it degrades the hole mobility. Most of the methods to induce uniaxial stress in the device channel are such that they are beneficial to one type of transistor (for e.g. NFET), while it degrades the performance of the complementary transistor (in this case, PFET). Hence, one cannot use existing techniques which employ uniaxial stress to simultaneously improve both NFET and PFET device performance.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.    U.S. Pat. No. 6,717,216 and U.S. Pat. No. 6,884,667: Field effect transistor with stressed channel and method for making same—Inventor: Doris, Bruce B.    US20050085022A1 and US20050139930A1 Strained dislocation-free channels for CMOS and method of manufacture—Inventor: Chidambarrao, Dureseti.    US20050145837A1: Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain—Inventor: Chan, Victor.    U.S. Pat. No. 6,884,667: Field effect transistor with stressed channel and method for making same—Inventor: Doris, Bruce B.    US20050139929A1: Transistor design and layout for performance improvement with strain—Inventor: Rost, Timothy A.    U.S. Pat. No. 6,900,502: Strained channel on insulator device—Inventor: Ge, Chung-Hu.    U.S. Pat. No. 6,841,430: Semiconductor and fabrication method thereof—Inventor: Sugawara, Minoru.    US20040026765A1: Semiconductor devices having strained dual channel layers—Inventors: Currie et al.    U.S. Pat. No. 6,690,043: Semiconductor device and method of manufacturing the same—Inventor: Usuda, Koji.    US20020074598A1: Methodology for control of short channel effects in MOS transistors—Inventor: Doyle, Brian S.    U.S. Pat. No. 6,563,152: Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel—Inventor: Roberds, Brian.    US20020190344A1: Semiconductor device having a ghost source/drain region and a method of manufacture therefor—Inventor: Michejda, John A.    U.S. Pat. No. 6,274,913: Shielded channel transistor structure with embedded source/drain junctions—Inventor: Brigham, Lawrence.    US20020074598A1: Methodology for control of short channel effects in MOS transistors-:—Inventor: Doyle, Brian S.